1. Field of the Invention
The present invention relates to a voltage level converter circuit for converting the level of an input voltage.
2. Description of the Background Art
A flash memory must have a voltage of various levels applied to the memory cell. For example, in a DINOR type flash memory, various levels of voltages as shown in the following Table 1 must be applied corresponding to each operation mode.
TABLE 1 ______________________________________ Operation Mode Bit Line Word Line Source Line ______________________________________ Program 6 V/0 V -11 V/0 V Floating Erase Floating 12 V/0 V -11 V Read 1 V 3.3 V/0 V 0 V ______________________________________
In Table 1, the voltage to the left of the slash (/) sign indicates the level of the voltage applied in a selected state. The voltage to the right of the slash sign indicates the level of the voltage to be applied in a nonselected state.
A voltage level converter circuit for converting the voltage level is required to supply a voltage of different levels.
FIG. 29 is a circuit diagram showing a structure of a conventional voltage level converter circuit. Referring to FIG. 29, the voltage level converter circuit includes P channel MOS transistors P1 and P2, N channel MOS transistors N1 and N2, an inverter I1, a power supply voltage node nVcc, and nodes nVIN, nVN, n1 and n2.
The operation of this voltage level converter circuit will be described hereinafter.
When voltage Vin supplied to node nVIN attains a high (H) level (logical high: 3.3 V), P channel MOS transistor P1 is turned on and P channel MOS transistor P2 is turned off. This causes node n1 to be pulled up to the level of power supply voltage Vcc (here, 3.3 V), whereby N channel MOS transistor N2 is turned on. In response, node n2 attains the level of voltage VNN that is supplied to node nVN (here, 11 V), whereby N channel MOS transistor N1 is turned off.
When voltage Vin attains a low (L) level (logical low: 0 V), P channel MOS transistor P1 is turned off and P channel MOS transistor P2 is turned on. This causes node n2 to be driven to the level of power supply voltage Vcc (here, 3.3 V), whereby N channel MOS transistor N1 is turned on. In response, node n1 attains the level of voltage VNN (here, -11 V) supplied to node nVN, whereby N channel MOS transistor N2 is turned off.
The above-described operation can be summarized as in the following Table 2.
TABLE 2 ______________________________________ VNN Vin P1 P2 N1 N2 n1(Vout) n2 ______________________________________ -11 V H(3.3 V) On Off Off On Vcc(3.3 V) VNN(-11 V) L(0 V) Off On On Off VNN(-11 V) Vcc(3.3 V) ______________________________________
A circuit that can set voltage Vout output from node n1 to the level of power supply voltage Vcc (3.3 V) or voltage VNN (-11 V) depending upon the H/L of voltage Vin supplied to node nVIN is called a voltage level converter circuit.
A circuit that converts the voltage level by switching cross-coupled N channel MOS transistors N1 and N2 as shown in FIG. 29 is called a CVSL (Cascade Voltage Switch Logic).
However, usage of this CVSL causes a high voltage across the source and drain of N channel MOS transistors N1 and N2. Hot electrons will be generated to deteriorate the switching operation. There was a problem that the reliability of the transistor is degraded.
For example, in the conventional voltage level converter circuit of FIG. 29, a voltage of 14.3 V is applied across the source and drain of N channel MOS transistor N1 that is OFF when voltage Vin attains an H level.